The invention relates to an address transition detector (ATD) for a memory device, and more particularly, to an address transition detector which detects a change in address information in order to produce a timing signal.
Referring to FIG. 1, a conventional semiconductor memory device 100 comprises a memory cell array 1, a decoder 2, a sense amp 3, an ATD 4 and a clock generator circuit 5.
The memory cell array 1 includes a plurality of memory cells, not shown, which are disposed in a plurality of rows and columns. Memory cells in respective rows and respective columns are connected to corresponding ones of a plurality of word lines and bit lines. The decoder 2 is connected to the memory cell array 1 and receives an address signal from a control circuit, not shown. Specifically, the decoder 2 activates one of the word lines and one of the bit lines in accordance with the address signal to select a memory cell within the memory cell array 1. The sense amp 3 is connected to the memory cell array 1. Information stored in the selected memory cell of the array 1 is read out in terms of a change in the potential of the bit line, and is then fed to the sense amp 3. The ATD 4 receives the address signal and detects a change therein to produce a timing signal, which is used to align the timing of the operation of the memory cell array 1 and the sense amp 3 with the timing of the change in the address signal. The clock generator circuit 5 is connected to the ATD 4 and receives a timing signal therefrom, and is also connected to the memory cell array 1 and the sense amp 3 to produce and clock signals in response to the timing signal which determine the timing of the operation of the array 1 and the sense amp 3.
A conventional ATD 4 will be described with reference to FIGS. 2 and 3, which are a circuit diagram of the ATD 4 and timing diagrams illustrating the operation thereof, respectively.
As shown in FIG. 2, the ATD 4 includes a number of detection circuit 4a and a shaper circuit 4b connected in series, which are equal in number to the number of bits in the address signal, it being understood that only one such series combination is shown. The detection circuit 4a produces a detection signal indicating the occurrence of a change in the address signal. The shaper circuit 4b receives the detection signal from the detection circuit 4a, and removes noise waveforms from the detection signal to deliver a shaped timing signal. A logical sum of the output signals from the individual shaper circuits 4b is formed to define a timing signal the ATD 4.
The detection circuit 4a includes an EXOR gate E1 and a delay element D1. The EXOR gate E1 has a first input terminal which directly receives the address signal and a second input terminal which is connected to the first terminal by way of the delay element D1. The delay element D1 has an input terminal connected to the first input terminal of the EXOR gate E1 and an output terminal connected to the second input terminal of the EXOR gate E1. The delay element D1 applies a given time delay to the address signal to provide a delayed address signal. The EXOR gate E1 delivers a detection signal of a high level whenever the two input signals are different from each other. Thus, the detection signal from the EXOR gate E1 rises in response to a transition in the address signal and falls when a delay time t1 of the delay element D1 passes thereafter, as shown in FIG. 3.
The shaper circuit 4b includes a delay element D2, a NAND gate N1 and an inverter I1. The NAND gate N1 has a first input terminal connected to the output terminal of EXOR gate E1 and a second input terminal connected to its own first input terminal through the delay element D2. The delay element D2 has an input terminal connected to the output terminal of the EXOR gate E1 and an output terminal connected to the second input terminal of NAND gate N1. The delay element D2 applies a given time delay to the detection signal it receives from the EXOR gate E1. The NAND gate N1 receives the detection signal from the detection circuit 4a at its first input terminal and receives a delayed detection signal through the delay element D2 at its second input terminal. An output signal from the NAND gate N1 is passed through the inverter I1 and delivered as a shaped signal. When the two input signals to the NAND gate N1 are high, the shaped signal is high. Thus, the shaped signal rises with a delay corresponding to the delay time t2 of the delay element D2 with respect to the rising edge of the detection signal, as will be noted from FIG. 3. Thus when the detection signal has a pulse width less than delay time t2, the shaper circuit 4b removes this pulse by regarding it as noise. Hence, if an inversion occurs temporarily in the detection signal as a result of noise being mixed with the address signal, the influence of such noise upon the shaped signal or timing signal is prevented.
If a temporary inversion of the address signal which is attributable to noise occurs, the detection signal contains two pulses, each rising at a timing when the resulting address signal falls and at a later timing which is delayed by the delay time t1 of the delay element D1 with respect to such fall. These two pulses are formed in the detection signal when the interval of inversion of the address signal is less than the delay time t1 of the delay element D1. When each pulse in the detection signal has a width greater than the delay time t2 of the delay element D2 in the shaper circuit 4b, the shaper circuit 4b is no longer capable of completely removing a pulse which occurs in the detection signal attributable to a noise. If the clock generator circuit 5 produces a clock signal based on a timing signal which results from such a shaped signal, a malfunctioning of the memory cell array 1 and the sense amp 3 may result. In such instance, data from the memory cell array 1 cannot be read correctly.
As an example, the sense amp 3 operates to detect a variation in the potential on the bit line as it is charged and discharged with a period which complies with the capacitance of the bit line and the rate of response of the memory cell array 1. However, if a clock signal were produced in response to a timing signal which is influenced by a noise or noises which occur indefinitely in time, the data read by the sense amp 3 in a stable manner is inhibited.
It is an object of the invention to provide an address transition detection circuit with an improved noise resistance.